On October 19, MemSilicon, a portfolio company of Lenovo Capital and Incubator Group, announced it had closed a Series A round of more than 400 million yuan. Boyuan Capital led the round, with participation from Robert Bosch Venture Capital, Chuangling Capital, miHoYo, Zhongguancun Science City Company and GigaDevice. Existing backers Furong Investment, Guokai Kechuang, Hengyu Capital, Jinqiu Fund, Shunxi Fund, Xiaomi's strategic investment arm and CASSTAR all added to their positions. The proceeds will go mainly toward industrializing and commercializing RRAM, along with R&D on a new product line, the LPU.

MemSilicon also said Lu Tao, formerly president of Graphcore and its general manager for Greater China, has joined as CEO and co-founder. The company is overhauling its strategy: alongside continued work on commercializing resistive RAM (RRAM), it is starting development of a first-generation LPU aimed at large-model inference, pitched as a next-generation inference engine built around "full-strength models, high-speed tokens, and class-beating price-performance."

Why Now: From Peak Computing Power to Task Completion Efficiency

As the Agentic AI era arrives, AI deployment is shifting from question-answering to completing complex, long-horizon tasks. The key competitive metric in the next phase will move from peak computing power to task completion efficiency.

A single task can involve multiple rounds of inference, tool calls and context reuse, and may spin up several agents working in parallel. What customers want is not simply more tokens, but faster decoding and output at a given quality level, more tasks running concurrently, and a lower cost per task. That demands architectural innovation in inference systems, with compute, memory, interconnect and scheduling optimized together. Memory-compute coordination is seen as one of the core ways through.

This is not abstract. Where caching is effective, input cache hit rates run from 84.6% to 99.5%, while decoding accounts for 91.0% to 98.6% of LLM execution time (source: arxiv2605.26297v2, Agentic AI Workload Characterization). In other words, most of the time a user spends waiting for an agent to finish a task goes into shuttling data token by token.

Lu Tao spent more than 20 years in the chip industry before joining MemSilicon. He previously served as vice president at Lightelligence, president and Greater China general manager at Graphcore, and China general manager at Cavium, with a long-running focus on core AI infrastructure components: Arm-based server CPUs, DPUs, RDMA network cards, data center switch chips, large-SRAM IPUs for AI, NPUs built on 3D-stacked DRAM, and silicon photonics. That gives him a combined technical, product and commercial vantage point.

Large-model inference, he argues, is entering a critical period of architectural innovation. Pushing on a single dimension of performance no longer satisfies the combined demand for low latency, long context and high throughput, and memory-compute coordination is one of the core paths through.

"MemSilicon's positioning is clear," Lu said. "We're not getting into a race to the bottom with GPUs. We're focused on delivering high-speed tokens on full-strength models, serving the high-end inference market with class-beating price-performance."

As he sees it, large-model inference poses a new problem: run a model at full capability while still responding promptly at an affordable cost. That, he says, is uncharted territory for both general-purpose GPU architectures and pure-SRAM designs. "If you're exploring a new continent, you can't rely on the old map of simply adding more compute units, more memory density, more communication bandwidth. You have to rethink the system-level questions: what to compute, where to compute it, how to store the weights, how to move the data."

Drawing on China's deep strategic bench in memory, plus its own experience in AI chip product definition and commercial deployment, MemSilicon is pursuing RRAM commercialization and next-generation LPU development in parallel to speed up memory-compute coordination in the field.

The MemSilicon team grew out of the research group of Academician Liu Ming at the Chinese Academy of Sciences, with more than two decades of work on foundational technologies spanning materials, devices, processes and chip design. Starting from materials and device physics, the team's work extends into reliability, process integration, IP and chip design, and on to tape-out validation and applications. Beyond RRAM, it also has deep research experience in 3D integration, near-memory computing and hybrid compute-in-memory architectures.

Breaking the constraints of the von Neumann architecture and the bottlenecks of memory and data movement has been MemSilicon's founding goal throughout. Lu Tao brings system architecture perspective, industry ecosystem relationships and commercialization experience, which complement the team's foundational technology base. Together, the two should accelerate memory-compute coordination products from technical validation to commercial delivery.

The First-Generation LPU: Fix Data Movement First, Then Talk About Computing Power

Lu disclosed that MemSilicon has begun development of its first-generation LPU, targeting the core requirements of the Agentic AI era: low latency, long context and high throughput.

Tokens in the inference market are stratifying: the standard tier competes on cost, while the premium tier competes on experience and the business logic it will enable. MemSilicon is focused on serving large-model inference demand with a new generation of computing power foundation.

The decoding stage of large-model inference is fundamentally a memory-movement-intensive workload: every token generated requires repeatedly moving model weights and KV cache data, a bottleneck that stacking compute in isolation cannot solve. Adding GPUs can cut latency to a degree, but it also drives up power consumption, network complexity and cost per unit of service. Batch-heavy serving can lift throughput, yet it makes user-facing agents feel slower.

Rather than chasing compute specs in isolation, as traditional AI chips do, MemSilicon's LPU builds on memory technology and memory architecture innovation, optimizing compute, memory and interconnect together at the system level to address the large-model inference bottleneck.

"We want tokens to become a means of production everyone can afford," Lu said. "Faster responses, lower cost."

He noted that as large models, autonomous agents and embodied intelligence take on more continuous, more complex and even physical-world long-horizon tasks, low latency will shift from a nice-to-have to a precondition for whether a new business works at all. "In critical scenarios, a timeout is a failure. So when customers measure the value of inference, they will care more and more about the timeliness-to-cost ratio of a token."

"Our LPU starts from the memory architecture and optimizes compute and interconnect alongside it, so every user gets high-speed tokens while the model retains full capability, with system throughput and overall cost both accounted for. That's the first-stage goal for the MemSilicon LPU."

This round and the accompanying strategy shift mark a pivotal step in MemSilicon's move from an RRAM technology company to a memory-compute coordination chip company. With Lu Tao on board, a clearer strategic direction and backing from both industry and capital, MemSilicon aims to connect research, academia, industry, end users and investors end to end, turning its accumulated technology into verifiable, deliverable products and commercial value.