Zhongxingwei, a Chinese interconnect chip maker, recently held a brand and full-stack product launch in Wuxi, showing its full-scenario high-performance interconnect chip platform for the first time. The platform is organized around two tracks, general-purpose computing interconnect and AI computing interconnect, and covers storage, networking, IO expansion and AI cluster interconnect. Cumulative shipments now exceed 800,000 chips, and the company's products have been designed into offerings from Inspur, Lenovo, H3C and ZTE. At the event, Zhongxingwei also signed strategic agreements with seven industry partners — Kylin, UnionTech, Tencent Cloud, Inspur, H3C, ZTE and Lenovo — to align interconnect chips with operating systems and server platforms and speed up deployment of domestic high-performance interconnect solutions.

The contest in AI computing power plays out between chips as much as inside them. A high peak figure on a single chip says little about what a cluster of hundreds or thousands of them will actually deliver. How fast data moves, and how well compute, storage and networking work together, shapes the performance of the whole system. As AI clusters grow, interconnect has stopped being plumbing attached to the hardware and become one of the factors that decides whether computing power can be fully used. Zhongxingwei is one of the few Chinese interconnect chip companies with a full-stack footprint spanning core IP, chip development, and software, hardware and system integration, which makes it a useful case study in how domestic players are trying to chip away at the advantage overseas vendors hold in the high-end interconnect market.

Choosing a Compute System Takes More Than Single-Point Performance

For anyone building computing power infrastructure, picking an interconnect chip is not a matter of lining up bandwidth and latency numbers. The question is whether the product can meet real workload requirements and run reliably inside a complex system.

Inside an AI cluster, the compute hardware runs the calculations, but the data generated during training and inference has to keep moving between compute devices, storage systems and the network. If interconnect bandwidth is too low, latency too high, or device-to-device communication inefficient, compute resources end up waiting on data and hardware utilization suffers. Zhongxingwei sums up effective cluster computing power as "single-node computing power × scale × interconnect efficiency" — a formula that looks at the cluster as a whole, lays out the multiple factors shaping infrastructure performance, and gives enterprises one lens for evaluating interconnect options.

Different workloads emphasize different things. In AI clusters, device-to-device communication efficiency directly affects how large-scale compute jobs run. In cloud and storage systems, network throughput, IO performance and response latency govern data transfer, storage access and transaction processing respectively. The metrics buyers care about shift with the scenario, but in every case the product has to be assessed inside the actual system.

Beyond performance specs, three other factors determine whether an interconnect product makes it into enterprise-grade deployment.

The first is operational reliability. For enterprise computing power infrastructure, hitting performance targets in the lab is only the opening step. Whether a product stays stable and keeps data moving under complex loads and long run times weighs just as heavily in a buyer's decision.

The second is compatibility. An interconnect chip has to satisfy the relevant interface and protocol requirements, and also work alongside different CPU platforms, operating systems, drives, optical modules, communication libraries and server architectures. The broader the validated compatibility list, the easier it is for customers to slot the product into existing systems.

The third is production maturity and sustained supply. For server OEMs and infrastructure builders, a chip that has been designed and brought up is not yet ready for volume use. Stable mass production, reliable supply, and follow-on technical support and product iteration all determine whether a customer can keep deploying and upgrading systems.

Competition in high-performance interconnect chips, then, runs on two tracks: the performance of the silicon itself, and the product's reliability, integration efficiency and supply continuity in real systems. What customers ultimately weigh is not whether one spec leads the field, but whether the whole interconnect solution fits the business and can keep the system running over the long haul.

From Single Products to Full-Scenario Supply

Meeting compute systems' demands around performance, reliability, compatibility and sustained delivery requires a product line that spans different application scenarios.

Zhongxingwei splits its portfolio into general-purpose computing interconnect and AI computing interconnect. The first covers storage, networking and IO expansion needs in servers and storage systems; the second targets next-generation AI infrastructure with high-speed PCIe switching, InfiniBand networking and multi-protocol AI network cards. From basic interconnect to high-speed AI cluster links, the company has 12 products in volume production, addressing data transfer needs at different layers of a compute system.

On the general-purpose computing side, Zhongxingwei has built HBA cards, RAID cards, RoCE network cards and PCIe switch chips around storage, networking and IO expansion. The HBA cards handle connections between hosts and storage devices, while the RAID cards cover storage organization, IO processing and data protection.

At the launch, Zhongxingwei said its RAID products use in-house silicon and firmware, tuned jointly through data algorithms and intelligent IO interrupt coalescing, and are aimed at databases and high-redundancy storage. Read performance is on par with solutions from Broadcom, the global interconnect leader, and in a 16-drive RAID5 configuration running 256KiB sequential writes, write bandwidth came in up to 47% higher. The company also disclosed figures for its multi-mode RAID chip: data transfer bandwidth and IOPS both roughly 8x the previous generation, and about 2x the performance of advanced overseas products.

In networking, Zhongxingwei has shipped 10G, 25G and 100G network cards aimed at high-throughput, low-latency and RDMA workloads. For IO expansion, its PCIe switch chips use a self-developed CrossBar architecture supporting non-blocking switching, with support for the NCCL, RCCL, MCCL and ECCL communication libraries. According to the launch, measured performance is a drop-in match for Broadcom's PEX89104.

In AI interconnect, Zhongxingwei already offers PCIe switch chips, 400G IB network cards and IB switch chips. The PCIe switches extend connectivity and data exchange across multiple GPUs, while the 400G IB cards and switch chips serve high-bandwidth, low-latency cluster networks. At this launch the company added a PCIe 6.0 Switch and an 800G multi-protocol AI NIC, pushing its lineup into higher-bandwidth device interconnect and network communication.

The C82-4G chip Zhongxingwei introduced is China's first PCIe 6.0 Switch, supporting up to 144 lanes of PCIe 6.0 at 64 GT/s per lane, double PCIe 5.0. As AI servers pack in more GPUs and other compute devices, systems need not only higher-bandwidth links but more flexible interconnect topologies. Alongside the per-lane bandwidth gain, the C82-4G supports Fabric networking and CXL memory pooling, backing multi-GPU scale-out and more complex compute architectures.

The other headline product is the 800G multi-protocol AI NIC, also a domestic first. It integrates a 48-lane PCIe Gen6 switch, is tightly matched to Hygon CPUs and next-generation super-node Compute Tray architecture, supports RoCE v2 and VeRoCE protocol offload, and offers hardware-level per-packet spraying, out-of-order reassembly, selective retransmission and programmable congestion control. Compared with the existing 400G IB cards and IB switch chips, it lifts network bandwidth to 800G, supports both IB and RoCE modes, and folds in PCIe switching, aimed at the high-bandwidth, low-latency communication demands of next-generation super nodes.

From general-purpose to AI computing, each scenario places different demands on interconnect performance, protocols and system architecture. For server OEMs, getting storage, networking and compute devices to work together efficiently while accommodating varied customer hardware configurations and deployment needs is a central design problem, and Zhongxingwei's coverage across multiple interconnect layers gives them more options in system design and integration. For cloud and AI infrastructure customers, it means being able to match an interconnect approach to their own compute scale, system architecture and business needs, covering current deployments while leaving room for later expansion and architectural upgrades.

More Than 400,000 Chips Shipped in a Year, With Core IP Developed In-House

From volume shipments of existing products to a new generation of high-bandwidth silicon, Zhongxingwei keeps pushing out its product boundaries. Behind that sit sustained R&D spending, market-tested products, experience delivering at scale, and ecosystem compatibility work across a range of software and hardware platforms.

Zhongxingwei has kept a relatively low profile in the industry. In practice it has assembled a sizeable R&D organization: more than 1,000 R&D staff, with technical personnel accounting for over 90% of headcount, spread across eight R&D centers in Wuxi, Tianjin, Hefei, Changsha, Chengdu, Shenzhen and Xi'an. The company develops its core IP and architectures in-house, with continued investment in high-speed interfaces, low-latency forwarding architectures and high-speed SerDes driving successive product generations.

On reliability, Zhongxingwei has built RAS mechanisms spanning the full data path, with end-to-end data protection, redundancy and automatic failover to improve stability. Its products are manufactured on domestic process nodes, and from core IP and chip architecture through to the supply chain, the company says it has a self-controlled technology stack. Looking to next-generation computing power infrastructure, it is also working on optical interconnect, high-speed SerDes and storage pooling, pushing domestic high-performance interconnect toward higher bandwidth and lower latency.

Whether that technical base translates into market position depends on how the products hold up at scale. Zhongxingwei disclosed cumulative shipments of more than 400,000 chips across its portfolio in 2025, with sales above 1 billion yuan. Since founding, total shipments have passed 800,000 units, including more than 100,000 network cards, more than 400,000 storage cards and more than 300,000 switch chips.

In the field, Zhongxingwei's HBA cards and network cards have been deployed at scale in telecom carrier operations, with nearly 100,000 units in service and more than 18 months of stable operation in network cloud environments. Storage architectures built on its RAID products meet the microsecond latency and million-level concurrent IOPS requirements of the financial sector, and on the strength of a fully domestic stack have been deployed in volumes above 50,000 units. The company said its chips run below 100 DPPM (defects per million) — fewer than 100 returns per million chips shipped — and that analysis of those returns found none of the issues originated in the chips themselves.

At the same time, interconnect chips have to work with servers, CPUs, operating systems and storage and networking components, so platform compatibility and ecosystem integration also shape how quickly products can be deployed. Zhongxingwei has completed compatibility work with seven major CPU platforms and partnered with 15-plus mainstream compute chips, 15-plus mainstream cloud platforms, more than 50 operating system partners and over 300 drive and optical module partners, building out an ecosystem network across multiple hardware and software layers.

For China's high-performance interconnect chip industry, control over core technology is the baseline; volume shipments, stable operation and compatibility in messy real-world software and hardware environments decide whether a product actually gets into computing power infrastructure. Zhongxingwei has put together a capability set spanning in-house development, reliability engineering, volume delivery and ecosystem integration, pairing self-controlled interconnect products with a record of shipping and deploying them at scale.

Closing Thoughts: Can a "Chinese Broadcom" Emerge?

Globally, the strength of leading interconnect vendors such as Broadcom rests not on any single chip but on product portfolios, technical depth and customer ecosystems accumulated over decades. For Zhongxingwei to become a bellwether high-performance interconnect supplier in China's computing power chain, it still has to prove itself through more advanced product generations, validation in demanding scenarios and large-scale commercial use.

Still, from its full-stack footprint to its delivery volumes, Zhongxingwei has shown the foundation and the potential to head that way. Whether China's interconnect chip sector can produce a company with Broadcom-style all-round competitiveness will be one of the storylines worth watching as the country's computing power supply chain localizes.