On October 29, XHEART unveiled X7 Ultra, a chip built for large models, in Suzhou, and laid out the development targets for its next-generation chip, the X9.

CEO Li Zonglin summed up the company's approach in a single line on stage: "Let large models define chips, and let chips carry the next evolution of large models." Put another way: rather than starting from hardware specs, XHEART works backward from what real models need, then rearranges compute, memory, and data movement around that.

The headline number for X7 Ultra is 700 TOPS of computing power for large models. But the 700 was not really the point of the launch.

How the 700 TOPS Was Measured

The company says the 700 TOPS figure is not a paper number from a lab benchmark. It comes from evaluations on assisted-driving large models already in mass production, with one additional constraint: after quantized deployment, the model's output must match the output of the post-training FP32 floating-point model with more than 99.99% similarity.

That claim is worth unpacking. Quantized deployment compresses model weights from high precision down to fewer bits, which saves memory and bandwidth and runs faster, at the cost of some accuracy. A common pattern in the industry is a beautiful headline compute number that comes with enough accuracy loss to degrade model performance, which makes that computing power unusable in a production vehicle.

So the 99.99% similarity figure functions as a threshold: the 700 TOPS was achieved while model performance stayed essentially unchanged. TOPS itself measures trillions of integer operations per second, a throughput unit, and the share of it that actually keeps a model fed can vary widely between chips with the same rating.

Six Capabilities, Five of Them Aimed at Compute You Can't Actually Use

X7 Ultra lists six core capabilities spanning compute, precision, bandwidth, and system-level coordination.

First is an oversized NPU core: data exchange that traditionally happened between small cores at hundreds of GB/s is pulled inside a single core, where the interconnect runs at TB/s. The point is shortening the distance data has to travel, so it no longer shuttles back and forth between two cores.

Second is hardware-software co-design to raise parallelism, with NPU compute utilization measured at 98.7% on production models. Low utilization is a chronic problem for this class of chip, with computing power consumed by data movement, the issue the industry calls the memory wall. A figure of 98.7% means the large majority of the rated computing power is genuinely doing math.

Third is network-wide fusion: keeping intermediate results on-chip as much as possible to cut repeated reads and writes to external memory. This is another route to saving bandwidth.

Fourth, the chip carries China's first mass-produced Armv9 automotive-grade CPU. Fifth is deep heterogeneous computing, supporting LiDAR processing bandwidth of up to 20 million points per second and a 100% improvement in sensor pre-processing stability. Sixth is safety: the chip meets ISO 26262 ASIL-B requirements, and its built-in MCU is certified to ASIL-D. ASIL is the automotive functional safety rating scale, and D is the highest tier.

Three of the six, the first, second, and third, all address the same problem: keeping computing power from being wasted on data movement. With the architecture and the toolchain working together, X7 Ultra supports deployable models with 10 times the parameter count.

Mass Production in Two Years, 200,000 Units in Eight Months

Beyond the specs, the launch came with a fair amount of detail on production progress.

XHEART went from founding to chip mass production in two years. As of the launch, the X7 series had been in mass production for eight months, with cumulative shipments above 200,000 units, deployment in 10 production vehicle models, and orders for more than 40 models. An L3/L4 computing platform built on dual X7 chips has also won design wins across several vehicle programs, extending the company from driver assistance toward higher levels of autonomy.

Two guests joined on stage. Momenta CEO Cao Xudong publicly described the company's third insight for the first time, also framed as large models defining chips: he argued that chips defined by large models can deliver 10 times the performance of general-purpose chips, that L4 at scale will require models with tens to hundreds of billions of parameters, and that algorithms and chips have to be designed together. He mentioned the forthcoming R7 Ultra, built on X7 Ultra, with model parameters scaled up 5 to 10 times and safety performance improved by more than 5 to 10 times. He expects L3 and L4 to hit an important inflection point in 2028 and reach scale deployment by 2030.

Speaking in a panel session, Turing Award winner Jack Dongarra said algorithm, software, and chip teams should work closely together before a design is frozen, and that improving the efficiency of data movement inside a chip and between chips is a key direction for hardware-software co-optimization. TSMC Vice President Chen Ping said TSMC has provided process support for X7 Ultra.

The Next Generation Bets on World Models

X7 Ultra is not the end point. Aimed at the next generation of world models, the X9 targets 3,000 TOPS of computing power for large models and 700GB/s of single-chip memory bandwidth, with a planned launch in 2027.

Raising computing power and bandwidth together points somewhere specific: applications like world models have to predict what happens next, so compute and memory access scale up in tandem, and piling on computing power alone just runs into a bandwidth ceiling.

That also reflects a shift in how assisted-driving chips compete, moving from peak TOPS to a broader ledger of effective computing power, bandwidth, energy efficiency, toolchains, and validation in production. End-to-end systems and world models amplify compute and memory demands at the same time, forcing the co-design of algorithms, software, and chips earlier in the process. Delivery at volume has gone from a downstream step to a test of whether a technical roadmap holds up at all.